View LTC1408CUH-12_4424511.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

LTC1408-12 6 Channel, 12-Bit, 600ksps Simultaneous Sampling ADC with Shutdown DESCRIPTIO
The LTC(R)1408-12 is a 12-bit, 600ksps ADC with six simultaneously sampled differential inputs. The device draws only 5mA from a single 3V supply, and comes in a tiny 32 pin (5mm x 5mm) QFN package. A SLEEP shutdown feature further reduces power consumption to 6W. The combination of low power and tiny package makes the LTC1408-12 suitable for portable applications. The LTC1408-12 contains six separate differential inputs that are sampled simultaneously on the rising edge of the CONV signal. These six sampled inputs are then converted at a rate of 100ksps per channel. The 83dB common mode rejection allows users to eliminate ground loops and common mode noise by measuring signals differentially from the source. The device converts 0V to 2.5V unipolar inputs differentially, or 1.25V bipolar inputs also differentially, depending on the state of the BIP pin. Any analog input may swing rail-to-rail as long as the differential input range is maintained. The conversion sequence can be abbreviated to convert fewer than six channels, depending on the logic state of the SEL2, SEL1 and SEL0 inputs. The serial interface sends out the six conversion results in 96 clocks for compatibility with standard serial interfaces.
FEATURES

600ksps ADC with 6 Simultaneously Sampled Differential Inputs 100ksps Throughput per Channel 72dB SINAD Low Power Dissipation: 15mW 3V Single Supply Operation 2.5V Internal Bandgap Reference, Can be Overdriven with External Reference 3-Wire SPI-Compatible Serial Interface 0V to 2.5V Unipolar, or 1.25V Bipolar Differential Input Range SLEEP (6W) Shutdown Mode NAP (3.3mW) Shutdown Mode Internal Conversion Triggered by CONV 83dB Common Mode Rejection Tiny 32-Pin (5mm x 5mm) QFN Package
APPLICATIO S

Multiphase Power Measurement Multiphase Motor Control Data Acquisition Systems Uninterruptable Power Supplies
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 6084440, 6522187.
BLOCK DIAGRA
CH5- CH5+ CH4- CH4+ 21 20 19 18 17
CH3-
CH3+
CH2-
CH2+
CH1-
CH1+
CH0-
CH0+
10F VCC
16
15
14
12 13
11
10
9
8
7
6
5
4
24
-
-
S AND H
-
-
-
-
S AND H
S AND H
S AND H
S AND H
S AND H
600ksps 12-BIT ADC
MUX TIMING LOGIC 30 32 VREF 10F 23 29 BIP 26 27 28
235114 TA01
2.5V REFERENCE GND 22
33
U
W
U
3V VDD 25 12-BIT LATCH 0 12-BIT LATCH 1 12-BIT LATCH 2 12-BIT LATCH 3 12-BIT LATCH 4 12-BIT LATCH 5 OVDD 3V SD0 0.1F 2 OGND
+
+
+
+
+
+
THREESTATE SERIAL OUTPUT PORT
3 1
CONV SCK DGND
31
SEL2 SEL1 SEL0
140812f
1
LTC1408-12 ABSOLUTE
(Notes 1, 2)
AXI U
RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW
DGND CONV SEL0 SEL1 SEL2 SCK VDD BIP
Supply Voltage (VDD, VCC, OVDD) .............................. 4V Analog and VREF Input Voltages (Note 3) ................................... - 0.3V to (VDD + 0.3V) Digital Input Voltages .................. - 0.3V to (VDD + 0.3V) Digital Output Voltage .................. - 0.3V to (VDD + 0.3V) Power Dissipation .............................................. 100mW Operation Temperature Range LTC1408C-12 .......................................... 0C to 70C LTC1408I-12 ...................................... - 40C to 85C Storage Temperature Range ................. - 65C to 125C
ORDER PART NUMBER
24 VCC 23 VREF 22 GND 21 CH5- 20 CH5+ 19 GND 18 CH4- 17 CH4+
32 31 30 29 28 27 26 25 SDO OGND OVDD CH0+ CH0- GND CH1+ CH1- 1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16
GND GND GND CH2+ CH2- CH3+ CH3- GND
LTC1408CUH-12 LTC1408IUH-12
33
QFN PART MARKING
1408-12
TJMAX = 125C, JA = 34C/ W EXPOSED PIN IS GND (PAD 33) MUST BE SOLDERED TO PCB
QFN PACKAGE 32-PIN (5mm x 5mm) PLASTIC QFN
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
CO VERTER CHARACTERISTICS
PARAMETER Resolution (No Missing Codes) Integral Linearity Error Offset Error Offset Match from CH0 to CH5 Range Error Range Match from CH0 to CH5 Range Tempco
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. With internal reference, VDD = VCC = 3V.
CONDITIONS
MIN 12 -1 -4.5 -3 -12 -5

TYP 0.25 1 0.5 2 1 15 1
MAX 1 4.5 3 12 5
UNITS Bits LSB mV mV mV mV ppm/C ppm/C
(Note 5) (Note 4) (Note 4) Internal Reference (Note 4) External Reference
A ALOG I PUT
SYMBOL PARAMETER VIN VCM IIN CIN tACQ tAP tJITTER tSK CMRR
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. With internal reference, VDD = VCC = 3V.
CONDITIONS 2.7V VDD 3.3V (Note 8)
MIN
TYP 0 to 2.5 0 to VDD
MAX
UNITS V V
Analog Differential Input Range (Notes 3, 8, 9) Analog Common Mode + Differential Input Range Analog Input Leakage Current Analog Input Capacitance Sample-and-Hold Acquisition Time Sample-and-Hold Aperture Delay Time Sample-and-Hold Aperture Delay Time Jitter Channel to Channel Aperture Skew Analog Input Common Mode Rejection Ratio
1 13 39 1 0.3 200
(Note 6)
fIN = 100kHz, VIN = 0V to 3V fIN = 10MHz, VIN = 0V to 3V
-83 -67
140812f
2
U
A pF ns ns ps ps dB dB
W
U
U
WW
W
U
U
U
LTC1408-12
DY A IC ACCURACY
SYMBOL SINAD THD SFDR IMD PARAMETER Signal-to-Noise Plus Distortion Ratio Total Harmonic Distortion Spurious Free Dynamic Range Intermodulation Distortion Code-to-Code Transition Noise Full Power Bandwidth Full Linear Bandwidth
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. With internal reference, VDD = VCC = 3V.
CONDITIONS 100kHz Input Signal 300kHz Input Signal 100kHz First 5 Harmonics 300kHz First 5 Harmonics 100kHz Input Signal 300kHz Input Signal 0.625VP-P, 833kHz into CH0+, 0.625VP-P, 841kHz into CH0-. Bipolar Mode. Also Applicable to Other Channels VREF = 2.5V (Note 17) VIN = 2.5VP-P, SDO = 11585LSBP-P (-3dBFS) (Note 15) S/(N + D) 68dB, Bipolar Differential Input

I TER AL REFERE CE CHARACTERISTICS
PARAMETER VREF Output Voltage VREF Output Tempco VREF Line Regulation VREF Output Resistance VREF Settling Time External VREF Input Range CONDITIONS IOUT = 0
DIGITAL I PUTS A D DIGITAL OUTPUTS
SYMBOL VIH VIL IIN CIN VOH VOL IOZ COZ ISOURCE ISINK PARAMETER High Level Input Voltage Low Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage Low Level Output Voltage Hi-Z Output Leakage DOUT Hi-Z Output Capacitance DOUT Output Short-Circuit Source Current Output Short-Circuit Sink Current VOUT = 0V, VDD = 3V VOUT = VDD = 3V CONDITIONS VDD = 3.3V VDD = 2.7V VIN = 0V to VDD
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VDD = VCC = 3V.
MIN

U
U
U
WU U
MIN 70 -80
TYP 72 72 -90 -86 90 86 -80 0.2 50 5
MAX
UNITS dB dB dB dB dB dB dB LSBRMS MHz MHz
U
TA = 25C. VDD = VCC = 3V.
MIN TYP 2.5 15 600 0.2 2 2.55 VDD MAX UNITS V ppm/C V/V ms V
VDD = 2.7V to 3.6V, VREF = 2.5V Load Current = 0.5mA CREF = 10F
TYP
MAX 0.6 10
UNITS V V A pF V V V A pF mA mA
2.4
5 VDD = 3V, IOUT = - 200A VDD = 2.7V, IOUT = 160A VDD = 2.7V, IOUT = 1.6mA VOUT = 0V and VDD

2.5
2.9 0.05 0.4 10 1 20 15
140812f
3
LTC1408-12
POWER REQUIRE E TS
SYMBOL VDD, VCC IDD + ICC PARAMETER Supply Voltage Supply Current
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. With internal reference, VDD = VCC= 3V.
CONDITIONS Active Mode, fSAMPLE = 600ksps Nap Mode Sleep Mode Active Mode with SCK, fSAMPLE = 600ksps

PD
Power Dissipation
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VDD = 3V.
SYMBOL fSAMPLE(MAX) tTHROUGHPUT tSCK tCONV t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 PARAMETER Maximum Sampling Rate per Channel (Conversion Rate) Minimum Sampling Period (Conversion + Acquisiton Period) Clock Period Conversion Time Minimum High or Low SCLK Pulse Width CONV to SCK Setup Time SCK Before CONV Minimum High or Low CONV Pulse Width SCK to Sample Mode CONV to Hold Mode 96th SCK to CONV Interval (Affects Acquisition Period) Delay from SCK to Valid Bits 0 Through 11 SCK to Hi-Z at SDO Previous SDO Bit Remains Valid After SCK VREF Settling Time After Sleep-to-Wake Transition (Note 16) (Notes 6, 17) (Note 6) (Notes 6, 10) (Note 6) (Note 6) (Note 6) (Notes 6, 11) (Notes 6, 7, 13) (Notes 6, 12) (Notes 6, 12) (Notes 6, 12) (Notes 6, 14) 2 2 CONDITIONS

TI I G CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliabilty and lifetime. Note 2: All voltage values are with respect to ground GND. Note 3: When these pins are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents greater than 100mA below GND or greater than VDD without latchup. Note 4: Offset and range specifications apply for a single-ended CH0+ - CH5+ input with CH0 - - CH5- grounded and using the internal 2.5V reference. Note 5: Integral linearity is tested with an external 2.55V reference and is defined as the deviation of a code from the straight line passing through the actual endpoints of a transfer curve. The deviation is measured from the center of quantization band. Linearity is tested for CH0 only. Note 6: Guaranteed by design, not subject to test. Note 7: Recommended operating conditions. Note 8: The analog input range is defined for the voltage difference between CHx+ and CHx-, x = 0-5.
4
UW
MIN 2.7
TYP 3.0 5 1.1 2.0 15
MAX 3.6 7 1.9 15
UNITS V mA mA A mW
UW
MIN 100
TYP
MAX
UNITS kHz
10 100 96 2 3 0 4 4 1.2 45 8 6 10000 10000
s ns SCLK cycles ns ns ns ns ns ns ns ns ns ns ms
Note 9: The absolute voltage at CHx+ and CHx- must be within this range. Note 10: If less than 3ns is allowed, the output data will appear one clock cycle later. It is best for CONV to rise half a clock before SCK, when running the clock at rated speed. Note 11: Not the same as aperture delay. Aperture delay (1ns) is the difference between the 2.2ns delay through the sample-and-hold and the 1.2ns CONV to Hold mode delay. Note 12: The rising edge of SCK is guaranteed to catch the data coming out into a storage latch. Note 13: The time period for acquiring the input signal is started by the 96th rising clock and it is ended by the rising edge of CONV. Note 14: The internal reference settles in 2ms after it wakes up from Sleep mode with one or more cycles at SCK and a 10F capacitive load. Note 15: The full power bandwidth is the frequency where the output code swing drops by 3dB with a 2.5VP-P input sine wave. Note 16: Maximum clock period guarantees analog performance during conversion. Output data can be read with an arbitrarily long clock period. Note 17: The conversion process takes 16 clocks for each channel that is enabled, up to 96 clocks for all 6 channels.
140812f
LTC1408-12 TYPICAL PERFOR A CE CHARACTERISTICS
SINAD vs Input Frequency
74 71
THD, 2nd, 3rd (dB)
THD, 2nd, 3rd (dB)
68
SINAD (dB)
65 62 59 56 53 0.1
1 FREQUENCY (MHz)
SFDR vs Input Frequency
92 86 80 SFDR (dB) 74 68 62
56 77 74 71
MAGNITUDE (dB)
SNR (dB)
56 50 0.1
1 FREQUENCY (MHz)
100kHz Bipolar Sine Wave 8192 Point FFT Plot
0 -10 DIFFERENTIAL LINEARITY (LSB) -20 -30 MAGNITUDE (dB) -40 -50 -60 -70 -80 -90 -100 -110 -120 0 10 30 20 FREQUENCY (KHZ) 40 50
140812 G07
INTEGRAL LINEARITY (LSB)
UW
140814 G01
VDD = 3V, TA = 25C THD, 2nd and 3rd vs Input Frequency
-50 -56 -62 BIPOLAR SINGLE-ENDED
THD, 2nd and 3rd vs Input Frequency
-50 -56 -62 -68 -74 -80 -86 -92 -98 -104
10
UNIPOLAR SINGLE-ENDED
THD 2nd
-68 -74 -80 -86 -92 -98 -104
THD 2nd
3rd
3rd
-110 0.1
1 FREQUENCY (MHz)
10
140812 G02
-110 0.1
1 FREQUENCY (MHz)
10
140812 G03
SNR vs Input Frequency
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100
53 50 0.1 68 65 62 59
100kHz Unipolar Sine Wave 8192 Point FFT Plot
-110 -120
1 FREQUENCY (MHz) 10
140812 G05
10
140814 G04
0
10
30 20 FREQUENCY (kHz)
40
50
140812 G06
Differential Linearity vs Output Code, CH0, Unipolar Mode
1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 512 1024 1536 2048 2560 3072 3584 4096 OUTPUT CODE
140812 G08
Integral Linearity vs Output Code, CH0, Unipolar Mode
1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 0 0 512 1024 1536 2048 2560 3072 3584 4096 OUTPUT CODE
140812 G09
140812f
5
LTC1408-12 TYPICAL PERFOR A CE CHARACTERISTICS
Full Scale Signal Response
3 0 -3 -6
MAGNITUDE (dB)
-12 -15 -18 -21 -24 -27 -30 10 100 FREQUENCY (MHz) 1000
1408 G10
CMRR (dB)
-9
Crosstalk vs Frequency
0 -20
CROSSTALK (dB)
-40
PSRR (dB)
-60 -80 -100
-120 100 1k 10k 100k 1M 10M 100M 1G FREQUENCY (Hz)
1408 G12
6
UW
VDD = 3V, TA = 25C
CMRR vs Frequency
0 -20 -40 -60 -80 -100 -120 100
1k
10k 100k 1M 10M 100M 1G FREQUENCY (Hz)
1408 G11
PSRR vs Frequency
0 -20 -40 -60 -80 -100 -120 100
1k
10k 100k 1M 10M 100M 1G FREQUENCY (Hz)
1408 G13
140812f
LTC1408-12
PI FU CTIO S
SDO (Pin 1): Three-State Serial Data Output. Each set of six output data words represent the six analog input channels at the start of the previous conversion. Data for CH0 comes out first and data for CH5 comes out last. Each data word comes out MSB first. OGND (Pin 2): Ground Return for SDO Currents. Connect to the solid ground plane. OVDD (Pin 3): Power Supply for the SDO Pin. OVDD must be no more than 300mV higher than VDD and can be brought to a lower voltage to interface to low voltage logic families. The unloaded high state at SDO is at the potential of OVDD. CH0+ (Pin 4): Non-Inverting Channel 0. CH0+ operates fully differentially with respect to CH0- with a 0V to 2.5V, or 1.25V differential swing and a 0V to VDD absolute input range. CH0- (Pin 5): Inverting Channel 0. CH0- operates fully differentially with respect to CH0+ with a -2.5V to 0V, or 1.25V differential swing and a 0V to VDD absolute input range. GND (Pins 6, 9, 12, 13, 16, 19): Analog Grounds. These ground pins must be tied directly to the solid ground plane under the part. Analog signal currents flow through these connections. CH1+ (Pin 7): Non-Inverting Channel 1. CH1+ operates fully differentially with respect to CH1- with a 0V to 2.5V, or 1.25V differential swing and a 0V to VDD absolute input range. CH1- (Pin 8): Inverting Channel 1. CH1- operates fully differentially with respect to CH1+ with a -2.5V to 0V, or 1.25V differential swing and a 0V to VDD absolute input range. CH2+ (Pin 10): Non-Inverting Channel 2. CH2+ operates fully differentially with respect to CH2- with a 0V to 2.5V, or 1.25V differential swing and a 0V to VDD absolute input range. CH2- (Pin 11): Inverting Channel 2. CH2- operates fully differentially with respect to CH2+ with a -2.5V to 0V, or 1.25V differential swing and a 0V to VDD absolute input range. CH3+ (Pin 14): Non-Inverting Channel 3. CH3+ operates fully differentially with respect to CH3- with a 0V to 2.5V, or 1.25V differential swing and a 0V to VDD absolute input range. CH3- (Pin 15): Inverting Channel 3. CH3- operates fully differentially with respect to CH3+ with a -2.5V to 0V, or 1.25V differential swing and a 0V to VDD absolute input range. CH4+ (Pin 17): Non-Inverting Channel 4. CH4+ operates fully differentially with respect to CH4- with a 0V to 2.5V, or 1.25V differential swing and a 0V to VDD absolute input range. CH4- (Pin 18): Inverting Channel 4. CH4- operates fully differentially with respect to CH4+ with a -2.5V to 0V, or 1.25V differential swing and a 0V to VDD absolute input range. CH5+ (Pin 20): Non-Inverting Channel 5. CH5+ operates fully differentially with respect to CH5- with a 0V to 2.5V, or 1.25V differential swing and a 0V to VDD absolute input range. CH5- (Pin 21): Inverting Channel 5. CH5- operates fully differentially with respect to CH5+ with a -2.5V to 0V, or 1.25V differential swing and a 0V to VDD absolute input range. GND (PIN 22): Analog Ground for Reference. Analog ground must be tied directly to the solid ground plane under the part. Analog signal currents flow through this connection. The 10F reference bypass capacitor should be returned to this pad. VREF (Pin 23): 2.5V Internal Reference. Bypass to GND and a solid analog ground plane with a 10F ceramic capacitor (or 10F tantalum in parallel with 0.1F ceramic). Can be overdriven by an external reference voltage between 2.55V and VDD, VCC. VCC (Pin 24): 3V Positive Analog Supply. This pin supplies 3V to the analog section. Bypass to the solid analog ground plane with a 10F ceramic capacitor (or 10F tantalum) in parallel with 0.1F ceramic. Care should be taken to place the 0.1F bypass capacitor as close to Pin 24 as possible. Pin 24 must be tied to Pin 25.
140812f
U
U
U
7
LTC1408-12
PI FU CTIO S
VDD (Pin 25): 3V Positive Digital Supply. This pin supplies 3V to the logic section. Bypass to DGND pin and solid analog ground plane with a 10F ceramic capacitor (or 10F tantalum in parallel with 0.1F ceramic). Keep in mind that internal digital output signal currents flow through this pin. Care should be taken to place the 0.1F bypass capacitor as close to Pin 25 as possible. Pin 25 must be tied to Pin 24. SEL2 (Pin 26): Most significant bit controlling the number of channels being converted. In combination with SEL1 and SEL0, 000 selects just the first channel (CH0) for conversion. Incrementing SELx selects additional channels(CH0-CH5) for conversion. 101, 110 or 111 select all 6 channels for conversion. Must be kept in a fixed state during conversion and during the subsequent conversion to read data. SEL1 (Pin 27): Middle significance bit controlling the number of channels being converted. In combination with SEL0 and SEL2, 000 selects just the first channel (CH0) for conversion. Incrementing SELx selects additional channels for conversion. 101, 110 or 111 select all 6 channels (CH0-CH5) for conversion. Must be kept in a fixed state during conversion and during the subsequent conversion to read data. SEL0 (Pin 28): Least significant bit controlling the number of channels being converted. In combination with SEL1 and SEL2, 000 selects just the first channel (CH0) for conversion. Incrementing SELx selects additional channels for conversion. 101, 110 or 111 select all 6 channels (CH0-CH5) for conversion. Must be kept in a fixed state during conversion and during the subsequent conversion to read data. BIP (Pin 29): Bipolar/Unipolar Mode. The input differential range is 0V - 2.5V when BIP is LOW, and it is 1.25V when BIP is HIGH. Must be kept in fixed state during conversion and during subsequent conversion to read data. When changing BIP between conversions the full acquisition time must be allowed before starting the next conversion. The output data is in 2's complement format for bipolar mode and straight binary format for unipolar mode. CONV (Pin 30): Convert Start. Holds the six analog input signals and starts the conversion on CONV's rising edge. Two CONV pulses with SCK in fixed high or fixed low state starts Nap mode. Four or more CONV pulses with SCK in fixed high or fixed low state starts Sleep mode. DGND (Pin 31): Digital Ground. This ground pin must be tied directly to the solid ground plane. Digital input signal currents flow through this pin. SCK (Pin 32): External Clock Input. Advances the conversion process and sequences the output data at SD0 (Pin1) on the rising edge. One or more SCK pulses wake from sleep or nap power saving modes. 16 clock cycles are needed for each of the channels that are activated by SELx (Pins 26, 27, 28), up to a total of 96 clock cycles needed to convert and read out all 6 channels. EXPOSED PAD (Pin 33): GND. Must be tied directly to the solid ground plane.
8
U
U
U
140812f
LTC1408-12
BLOCK DIAGRA
CH0+
4
CH0-
5 6
CH1+
7
CH1-
8 9
CH2
+
10
CH2-
11 12 13
CH3+
14
CH3-
15 16
CH4+
17
CH4-
18 19
CH5
+
20
CH5-
21
W
0.1F 10F VCC 24 3V VDD 25
+
S&H
- +
S&H
- +
S&H
-
MUX 600ksps 12-BIT ADC
+
S&H
12-BIT LATCH 0 12-BIT LATCH 1 12-BIT LATCH 2 12-BIT LATCH 3 12-BIT LATCH 4 12-BIT LATCH 5
OVDD 3V THREESTATE SERIAL OUTPUT PORT 3 SD0 1 OGND 2 0.1F
- +
S&H TIMING LOGIC 30 32 CONV SCK
- +
S&H
-
2.5V REFERENCE EXPOSED PAD 33 GND 22 10F BIP SEL2 SEL1 SEL0 VREF 23 29 26 27 28 31 DGND
1408 BD
140812f
9
t3
4 14 31 5 6 7 8 9 10 11 12 13 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 32 33
t1
t4
LTC1408-12
CONV
t6
HOLD
Back to SAMPLE mode if SELx = 000 Back to
INTERNAL S/H STATUS
t10
SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH0
SAMPLE
SCK
94
95
96
97
98
1
2
3
t8
SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH1
X
12-BIT DATA WORD
TI I G DIAGRA S
SDO
D11
12-BIT DATA WORD
Hi-Z
D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X
Hi-Z
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1
D0
X
X
tCONV
tTHROUGHPUT
34
51
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
52
53
54
55
56
57
58
59
60
61
62
63
64
65
to SAMPLE mode if SELx = 001
Back to SAMPLE mode if SELx = 010
SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH2 D9
12-BIT DATA WORD
SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH3
D11
D10
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
D11
D10
D9
D8
D7
D6
D5
D4
12-BIT DATA WORD
D3
D2
D1
D0
X
X
tCONV
tTHROUGHPUT
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
1
2
3
4
5
6
t6
t4
t6
Back to SAMPLE mode if SELx = 011
Back to SAMPLE mode if SELx = 100
t8
SAMPLE
t8
SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH4 D6
12-BIT DATA WORD
SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH5
D11
D10
D9
D8
D7
D5
D4
D3
D2
D1
D0
X
X
D11
D10
D9
D8
D7
D6
D5
D4
12-BIT DATA WORD
D3
D2
D1
D0
X
X
Hi-Z
D11
D10
D9
tCONV
tTHROUGHPUT
1408 TD01
W
D8
t9
t8
UW
10
LTC1408-12 Timing Diagram
t2
140812f
LTC1408-12
TI I G DIAGRA S
Nap Mode and Sleep Mode Waveforms
SCK
CONV
NAP
SLEEP
VREF
NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS
SCK t8 t10 SDO
W
UW
t1
t1
t11
1408 TD02
SCK to SDO Delay
SCK
VIH
VIH t9
VOH VOL
SDO
1408 TD03
Hi-Z
140812f
11
LTC1408-12
APPLICATIO S I FOR ATIO
SELECTING THE NUMBER OF CONVERTED CHANNELS (SEL2, SEL1, SEL0) These three control pins select the number of channels being converted (see Table 1). 000 selects only the first channel (CH0) for conversion. Incrementing SELx selects additional channels for conversion, up to 6 channels. 101, 110 or 111 select all 6 channels for conversion. These pins must be kept in a fixed state during conversion and during the subsequent conversion to read data. When changing modes between conversions, keep in mind that the output data of a particular channel will remain unchanged until after that channel is converted again. For example: convert a sequence of 4 channels (CH0, CH1, CH2, CH3) with SELx = 011, then, after these channels are converted change SELx to 001 to convert just CH0 and CH1. During the conversion of the first set of two channels you will be able to read the data from the same two channels converted as part of the previous group of 4 channels. Later, you could convert 4 or more channels to read back the unread CH2 and CH3 data that was converted in the first set of 4 channels. These pins are often hardwired to enable the right number of channels for a particular application. Choosing to convert fewer channels per conversion results in faster throughput of those channels. For example, 6 channels can be converted at 100ksps/ch, while 3 channels can be converted at 200ksps/ch.
Table 1. Conversion Sequence Control ("acquire" represents simultaneous sampling of all channels; CHx represents conversion of channels) SEL2 SEL1 SEL0 CHANNEL ACQUISITION AND CONVERSION SEQUENCE 0 0 0 acquire, CH0, acquire, CH0... 0 0 1 acquire, CH0, CH1, acquire, CH0, CH1... 0 1 0 acquire, CH0, CH1, CH2, acquire, CH0, CH1, CH2... 0 1 1 acquire, CH0, CH1, CH2, CH3, acquire, CH0, CH1, CH2, CH3... 1 0 0 acquire, CH0, CH1, CH2, CH3, CH4, acquire, CH0,CH1,CH2, CH3, CH4... 1 0 1 acquire, CH0, CH1, CH2, CH3, CH4, CH5, acquire, CH0, CH1, CH2, CH3, CH4, CH5... 1 1 0 acquire, CH0, CH1, CH2, CH3, CH4, CH5, acquire, CH0, CH1, CH2, CH3, CH4, CH5... 1 1 1 acquire, CH0, CH1, CH2, CH3, CH4, CH5, acquire, CH0, CH1, CH2, CH3, CH4, CH5...
12
U
BIPOLAR/UNIPOLAR MODE The input voltage range for each of the CHx input differential pairs is UNIPOLAR 0V - 2.5V when BIP is LOW, and BIPOLAR 1.25V when BIP is HIGH. This pin must be kept in fixed state during conversion and during subsequent conversion to read data. When changing BIP between conversions the full acquisition time must be allowed before starting the next conversion. After changing modes from BIPOLAR to UNIPOLAR, or from UNIPOLAR to BIPOLAR, you can still read the first set of channels in the new mode, by inverting the MSB to read these channels in the mode that they were converted in. DRIVING THE ANALOG INPUT The differential analog inputs of the LTC1408-12 may be driven differentially or as a single-ended input (i.e., the CHx- input is grounded). All twelve analog inputs of all six differential analog input pairs, CH0+ and CH0-, CH1+ and CH1-, CH2+ and CH2-, CH3+ and CH3-, CH4+ and CH4- and CH5+ and CH5-, are sampled at the same instant. Any unwanted signal that is common to both inputs of each input pair will be reduced by the common mode rejection of the sample-and-hold circuit. The inputs draw only one small current spike while charging the sample-and-hold capacitors at the end of conversion. During conversion, the analog inputs draw only a small leakage current. If the source impedance of the driving circuit is low, then the
140812f
W
UU
LTC1408-12
APPLICATIO S I FOR ATIO
LTC1408-12 inputs can be driven directly. As source impedance increases, so will acquisition time. For minimum acquisition time with high source impedance, a buffer amplifier must be used. The main requirement is that the amplifier driving the analog input(s) must settle after the small current spike before the next conversion starts (the time allowed for settling must be at least 39ns for full throughput rate). Also keep in mind while choosing an input amplifier the amount of noise and harmonic distortion added by the amplifier. CHOOSING AN INPUT AMPLIFIER Choosing an input amplifier is easy if a few requirements are taken into consideration. First, to limit the magnitude of the voltage spike seen by the amplifier from charging the sampling capacitor, choose an amplifier that has a low output impedance (< 100) at the closed-loop bandwidth frequency. For example, if an amplifier is used in a gain of 1 and has a unity-gain bandwidth of 50MHz, then the output impedance at 50MHz must be less than 100. The second requirement is that the closed-loop bandwidth must be greater than 40MHz to ensure adequate smallsignal settling for full throughput rate. If slower op amps are used, more time for settling can be provided by increasing the time between conversions. The best choice for an op amp to drive the LTC1408-12 depends on the application. Generally, applications fall into two categories: AC applications where dynamic specifications are most critical and time domain applications where DC accuracy and settling time are most critical. The following list is a summary of the op amps that are suitable for driving the LTC1408-12. (More detailed information is available in the Linear Technology Databooks and on the website at www.linear.com.)
LinearView is a trademark of Linear Technology Corporation.
U
LTC1566-1: Low Noise 2.3MHz Continuous Time Lowpass Filter. LT(R)1630: Dual 30MHz Rail-to-Rail Voltage FB Amplifier. 2.7V to 15V supplies. Very high AVOL, 500V offset and 520ns settling to 0.5LSB for a 4V swing. THD and noise are - 93dB to 40kHz and below 1LSB to 320kHz (AV = 1, 2VP-P into 1k, VS = 5V), making the part excellent for AC applications (to 1/3 Nyquist) where rail-to-rail performance is desired. Quad version is available as LT1631. LT1632: Dual 45MHz Rail-to-Rail Voltage FB Amplifier. 2.7V to 15V supplies. Very high AVOL, 1.5mV offset and 400ns settling to 0.5LSB for a 4V swing. It is suitable for applications with a single 5V supply. THD and noise are - 93dB to 40kHz and below 1LSB to 800kHz (AV = 1, 2VP-P into 1k, VS = 5V), making the part excellent for AC applications where rail-to-rail performance is desired. Quad version is available as LT1633. LT1801: 80MHz GBWP, -75dBc at 500kHz, 2mA/amplifier, 8.5nV/Hz. LT1806/LT1807: 325MHz GBWP, -80dBc distortion at 5MHz, unity gain stable, rail-to-rail in and out, 10mA/amplifier, 3.5nV/Hz. LT1810: 180MHz GBWP, -90dBc distortion at 5MHz, unity gain stable, rail-to-rail in and out, 15mA/amplifier, 16nV/Hz. LT1818/LT1819: 400MHz, 2500V/s, 9mA, Single/Dual Voltage Mode Operational Amplifier. LT6200: 165MHz GBWP, -85dBc distortion at 1MHz, unity gain stable, rail-to-rail in and out, 15mA/amplifier, 0.95nV/Hz. LT6203: 100MHz GBWP, -80dBc distortion at 1MHz, unity gain stable, rail-to-rail in and out, 3mA/amplifier, 1.9nV/Hz. LT6600: Amplifier/Filter Differential In/Out with 10MHz Cutoff frequency.
140812f
W
UU
13
LTC1408-12
APPLICATIO S I FOR ATIO
INPUT FILTERING AND SOURCE IMPEDANCE
The noise and the distortion of the input amplifier and other circuitry must be considered since they will add to the LTC1408-12 noise and distortion. The small-signal bandwidth of the sample-and-hold circuit is 50MHz. Any noise or distortion products that are present at the analog inputs will be summed over this entire bandwidth. Noisy input circuitry should be filtered prior to the analog inputs to minimize noise. A simple 1-pole RC filter is sufficient for many applications. For example, Figure 1 shows a 47pF capacitor from CHO+ to ground and a 51 source resistor to limit the net input bandwidth to 30MHz. The 47pF capacitor also acts as a charge reservoir for the input sampleand-hold and isolates the ADC input from sampling-glitch sensitive circuitry. High quality capacitors and resistors should be used since these components can add distortion. NPO and silvermica type dielectric capacitors have excellent linearity. Carbon surface mount resistors can generate distortion from self heating and from damage that may occur during soldering. Metal film surface mount resistors are much less susceptible to both problems. When high amplitude unwanted signals are close in frequency to the desired signal frequency a multiple pole filter is required. High external source resistance, combined with 13pF of input capacitance, will reduce the rated 50MHz input bandwidth and increase acquisition time beyond 39ns.
51*
ANALOG INPUT
1 47pF* 2
CH0+ CH0- LTC1408-12
3 10F 11 ANALOG INPUT 51* 4 47pF* 5
VREF
3.5V to 18V
GND CH1+ CH1-
1408 F01
*TIGHT TOLERANCE REQUIRED TO AVOID APERTURE SKEW DEGRADATION
Figure 1. RC Input Filter
14
U
INPUT RANGE The analog inputs of the LTC1408-12 may be driven fully differentially with a single supply. Either input may swing up to VCC, provided the differential swing is no greater than 2.5V with BIP (Pin 29) Low, or 1.25V with (BIP Pin 29) High. The 0V to 2.5V range is also ideally suited for singleended input use with single supply applications. The common mode range of the inputs extend from ground to the supply voltage VCC. If the difference between the CH+ and CH- at any input pair exceeds 2.5V (unipolar) or 1.25V (bipolar), the output code will stay fixed at positive fullscale, and if this difference goes below 0V (unipolar) or - 1.25V (bipolar), the output code will stay fixed at negative full-scale. INTERNAL REFERENCE The LTC1408-12 has an on-chip, temperature compensated, bandgap reference that is factory trimmed to 2.5V to obtain a precise 2.5V input span. The reference amplifier output VREF, (Pin 23) must be bypassed with a capacitor to ground. The reference amplifier is stable with capacitors of 1F or greater. For the best noise performance, a 10F ceramic or a 10F tantalum in parallel with a 0.1F ceramic is recommended. The VREF pin can be overdriven with an external reference as shown in Figure 2. The voltage of the external reference must be higher than the 2.5V of the open-drain P-channel output of the internal reference. The recommended range for an external reference is 2.55V to VDD. An external reference at 2.55V will see a DC quiescent load of 0.75mA and as much as 3mA during conversion.
LT1790-3 3V 10F 22 23 VREF LTC2351-12 GND
1408 F02
W
UU
Figure 2. Overdriving VREF Pin with an External Reference
140812f
LTC1408-12
APPLICATIO S I FOR ATIO
INPUT SPAN VERSUS REFERENCE VOLTAGE
The differential input range has a unipolar voltage span that equals the difference between the voltage at the reference buffer output VREF (Pin 23) and the voltage at ground. The differential input range of the ADC is 0V to 2.5V when using the internal reference. The internal ADC is referenced to these two nodes. This relationship also holds true with an external reference. DIFFERENTIAL INPUTS The ADC will always convert the difference of CH+ minus CH-, independent of the common mode voltage at any pair of inputs. The common mode rejection holds up at high frequencies (see Figure 3.) The only requirement is that both inputs not go below ground or exceed VDD.
0 -20 -40
STRAIGHT BINARY OUTPUT CODE
CMRR (dB)
-60 -80 -100
-120 100 1k 10k 100k 1M 10M 100M 1G FREQUENCY (Hz)
1408 G11
Figure 3. CMRR vs Frequency
2'S COMPLEMENT OUTPUT CODE
Integral nonlinearity errors (INL) and differential nonlinearity errors (DNL) are largely independent of the common mode voltage. However, the offset error will vary. DC CMRR is typically better than -90dB.
U
Figure 4 shows the ideal input/output characteristics for the LTC1408-12 in unipolar mode (BIP = Low). The code transitions occur midway between successive integer LSB values (i.e., 0.5LSB, 1.5LSB, 2.5LSB, FS - 1.5LSB). The output code is straight binary with 1LSB = 2.5V/4096 = 610V for the LTC1408-12. The LTC1408-12 has 0.2 LSB RMS of Gaussian white noise.
111...111 111...110 111...101 000...010 000...001 000...000 0 INPUT VOLTAGE (V)
1408 F04
W
UU
FS - 1LSB
Figure 4. LTC1408-12 Transfer Characteristic in Unipolar Mode (BIP = Low)
Figure 5 shows the ideal input/output characteristics for the LTC1408-12 in bipolar mode (BIP = High). The code transitions occur midway between successive integer LSB values (i.e., 0.5LSB, 1.5LSB, 2.5LSB, FS - 1.5LSB). The output code is 2's complement with 1LSB = 2.5V/4096 = 610V for the LTC1408-12. The LTC1408-12 has 0.2 LSB RMS of Gaussian white noise.
011...111 011...110 011...101
100...010 100...001 100...000 -FS INPUT VOLTAGE (V)
1408 F05
FS - 1LSB
Figure 5. LTC1408-12 Transfer Characteristic in Bipolar Mode (BIP = High)
140812f
15
LTC1408-12
APPLICATIO S I FOR ATIO
POWER-DOWN MODES
Upon power-up, the LTC1408-12 is initialized to the active state and is ready for conversion. The Nap and Sleep mode waveforms show the power down modes for the LTC1408-12. The SCK and CONV inputs control the power down modes (see Timing Diagrams). Two rising edges at CONV, without any intervening rising edges at SCK, put the LTC1408-12 in Nap mode and the power consumption drops from 15mW to 3.3mW. The internal reference remains powered in Nap mode. One or more rising edges at SCK wake up the LTC1408-12 very quickly and CONV can start an accurate conversion within a clock cycle. Four rising edges at CONV, without any intervening rising edges at SCK, put the LTC1408-12 in Sleep mode and the power consumption drops from 15mW to 6W. One or more rising edges at SCK wake up the LTC1408-12 for operation. The internal reference (VREF ) takes 2ms to slew and settle with a 10F load. Using sleep mode more frequently compromises the accuracy of the output data. Note that for slower conversion rates, the Nap and Sleep modes can be used for substantial reductions in power consumption. DIGITAL INTERFACE The LTC1408-12 has a 3-wire SPI (Serial Peripheral Interface) interface. The SCK and CONV inputs and SDO output implement this interface. The SCK and CONV inputs accept swings from 3V logic and are TTL compatible, if the logic swing does not exceed VDD. A detailed description of the three serial port signals follows:
16
U
Conversion Start Input (CONV) The rising edge of CONV starts a conversion, but subsequent rising edges at CONV are ignored by the LTC1408-12 until the following 96 SCK rising edges have occurred. The duty cycle of CONV can be arbitrarily chosen to be used as a frame sync signal for the processor serial port. A simple approach to generate CONV is to create a pulse that is one SCK wide to drive the LTC1408-12 and then buffer this signal to drive the frame sync input of the processor serial port. It is good practice to drive the LTC1408-12 CONV input first to avoid digital noise interference during the sample-to-hold transition triggered by CONV at the start of conversion. It is also good practice to keep the width of the low portion of the CONV signal greater than 15ns to avoid introducing glitches in the front end of the ADC just before the sample-and-hold goes into Hold mode at the rising edge of CONV. Minimizing Jitter on the CONV Input In high speed applications where high amplitude sine waves above 100kHz are sampled, the CONV signal must have as little jitter as possible (10ps or less). The square wave output of a common crystal clock module usually meets this requirement. The challenge is to generate a CONV signal from this crystal clock without jitter corruption from other digital circuits in the system. A clock divider and any gates in the signal path from the crystal clock to the CONV input should not share the same integrated circuit with other parts of the system. The SCK and CONV inputs should be driven first, with digital buffers
140812f
W
UU
LTC1408-12
APPLICATIO S I FOR ATIO
used to drive the serial port interface. Also note that the master clock in the DSP may already be corrupted with jitter, even if it comes directly from the DSP crystal. Another problem with high speed processor clocks is that they often use a low cost, low speed crystal (i.e., 10MHz) to generate a fast, but jittery, phase-locked-loop system clock (i.e., 40MHz). The jitter in these PLL-generated high speed clocks can be several nanoseconds. Note that if you choose to use the frame sync signal generated by the DSP port, this signal will have the same jitter of the DSP's master clock. The Typical Application Figure on page 20 shows a circuit for level-shifting and squaring the output from an RF signal generator or other low-jitter source. A single D-type flip flop is used to generate the CONV signal to the LTC1408-12. Re-timing the master clock signal eliminates clock jitter introduced by the controlling device (DSP, FPGA, etc.) Both the inverter and flip flop must be treated as analog components and should be powered from a clean analog supply. Serial Clock Input (SCK) The rising edge of SCK advances the conversion process and also udpates each bit in the SDO data stream. After CONV rises, the third rising edge of SCK sends out up to six sets of 12 data bits, with the MSB sent first. A simple approach is to generate SCK to drive the LTC1408-12 first and then buffer this signal with the appropriate number of inverters to drive the serial clock input of the processor serial port. Use the falling edge of the clock to latch data from the Serial Data Output (SDO) into your processor serial port. The 12-bit Serial Data will be received in six 16-bit words with 96 or more clocks per frame sync. If fewer than 6 channels are selected by SEL0-SEL2 for conversion, then 16 clocks are needed per channel to convert the analog inputs and read out the resulting data
U
after the next convert pulse. It is good practice to drive the LTC1408-12 SCK input first to avoid digital noise interference during the internal bit comparison decision by the internal high speed comparator. Unlike the CONV input, the SCK input is not sensitive to jitter because the input signal is already sampled and held constant. Serial Data Output (SDO) Upon power-up, the SDO output is automatically reset to the high impedance state. The SDO output remains in high impedance until a new conversion is started. SDO sends out up to six sets of 12 bits in the output data stream after the third rising edge of SCK after the start of conversion with the rising edge of CONV. The six or fewer 12-bit words are separated by two don't care bits and two clock cycles in high impedance mode. Please note the delay specification from SCK to a valid SDO. SDO is always guaranteed to be valid by the next rising edge of SCK. The 16 - 96-bit output data stream is compatible with the 16-bit or 32-bit serial port of most processors. BOARD LAYOUT AND BYPASSING Wire wrap boards are not recommended for high resolution and/or high speed A/D converters. To obtain the best performance from the LTC1408-12, a printed circuit board with ground plane is required. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track. If optimum phase match between the inputs is desired, the length of the twelve input wires of the six input channels should be kept matched. But each pair of input wires to the six input channels should be kept separated by a ground trace to avoid high frequency crosstalk between channels.
140812f
W
UU
17
LTC1408-12
APPLICATIO S I FOR ATIO
High quality tantalum and ceramic bypass capacitors should be used at the VCC, VDD and VREF pins as shown in the Block Diagram on the first page of this data sheet. For optimum performance, a 10F surface mount tantalum capacitor with a 0.1F ceramic is recommended for the VCC, VDD and VREF pins. Alternatively, 10F ceramic chip capacitors such as X5R or X7R may be used. The capacitors must be located as close to the pins as possible. The traces connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible. The VCC and VDD bypass capacitor returns to the ground plane and the VREF bypass capacitor returns to the Pin 22. Care should be taken to place the 0.1F VCC and VDD bypass capacitor as close to Pins 24 and 25 as possible. Figure 6 shows the recommended system ground connections. All analog circuitry grounds should be terminated at the LTC1408-12 Exposed Pad. The ground return from the LTC1408-12 to the power supply should be low impedance for noise-free operation. The Exposed Pad of the 32pin QFN package is also internally tied to the ground pads. The Exposed Pad should be soldered on the PC board to reduce ground connection inductance. All ground pins (GND, DGND, OGND) must be connected directly to the same ground plane under the LTC1408-12.
OVDD BYPASS, 0.1F, 0402
VDD BYPASS, 0.1F, 0402 VCC BYPASS, 0.1F, 0402 AND 10F, 0805
VREF BYPASS, 10F, 0805
Figure 6. Recommended Layout
18
U
HARDWARE INTERFACE TO TMS320C54x The LTC1408-12 is a serial output ADC whose interface has been designed for high speed buffered serial ports in fast digital signal processors (DSPs). Figure 7 shows an example of this interface using a TMS320C54X. The buffered serial port in the TMS320C54x has direct access to a 2kB segment of memory. The ADC's serial data can be collected in two alternating 1kB segments, in real time, at the full 600ksps conversion rate of the LTC1408-12. The DSP assembly code sets frame sync mode at the BFSR pin to accept an external positive going pulse and the serial clock at the BCLKR pin to accept an external positive edge clock. Buffers near the LTC1408-12 may be added to drive long tracks to the DSP to prevent corruption of the signal to LTC1408-12. This configuration is adequate to traverse a typical system board, but source resistors at the buffer outputs and termination resistors at the DSP, may be needed to match the characteristic impedance of very long transmission lines. If you need to terminate the SDO transmission line, buffer it first with one or two 74ACxx gates. The TTL threshold inputs of the DSP port respond properly to the 3V swing used with the LTC1408-12.
LTC1408-12 OVDD CONV 3 30 3V 5V TMS320C54x VCC BFSR SCK SDO OGND DGND 32 1 2 31 CONV CLK 3-WIRE SERIAL INTERFACE LINK
1408 F06
W
UU
BCLKR B11 B10 BDR
0V TO 3V LOGIC SWING
Figure 7. DSP Serial Interface to TMS320C54x
140812f
LTC1408-12
PACKAGE DESCRIPTIO U
UH Package 32-Lead Plastic QFN (5mm x 5mm)
(Reference LTC DWG # 05-08-1693)
0.70 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 5.00 0.10 (4 SIDES) PIN 1 TOP MARK (NOTE 6) 0.75 0.05 R = 0.05 TYP 0.00 - 0.05 BOTTOM VIEW--EXPOSED PAD R = 0.115 TYP 31 32 0.40 0.10 1 2 3.45 0.10 PIN 1 NOTCH R = 0.30 TYP OR 0.35 x 45 CHAMFER 3.50 REF (4-SIDES) 3.45 0.10
(UH32) QFN 0406 REV D
5.50 0.05 4.10 0.05 3.50 REF (4 SIDES) 3.45 0.05
3.45 0.05
0.200 REF NOTE: 1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE M0-220 VARIATION WHHD-(X) (TO BE APPROVED) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
0.25 0.05 0.50 BSC
140812f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC1408-12 RELATED PARTS
PART NUMBER ADCs LTC1402 LTC1403/LTC1403A LTC1405 LTC1407/LTC1407A LTC1408 LTC1411 LTC1412 LTC1420 LTC1608 LTC1609 LTC1864/LTC1865 LTC1864L/LTC1865L DACs LTC1592 LTC1666/LTC1667 LTC1668 References LT1460-2.5 LT1461-2.5 LT1790-2.5 Micropower Series Voltage Reference Precision Voltage Reference Micropower Series Reference in SOT-23 0.10% Initial Accuracy, 10ppm Drift 0.04% Initial Accuracy, 3ppm Drift 0.05% Initial Accuracy, 10ppm Drift 16-Bit, Serial SoftSpanTM IOUT DAC 12-/14-/16-Bit, 50Msps DAC 1LSB INL/DNL, Software Selectable Spans 87dB SFDR, 20ns Settling Time 12-Bit, 2.2Msps Serial ADC 12-/14-Bit, 2.8Msps Serial ADC 12-Bit, 5Msps Parallel ADC 12-/14-Bit, 3Msps Simultaneous Sampling ADC 14-Bit, 600ksps Simultaneous Sampling ADC 14-Bit, 2.5Msps Parallel ADC 12-Bit, 3Msps Parallel ADC 12-Bit, 10Msps Parallel ADC 16-Bit, 500ksps Parallel ADC 16-Bit, 250ksps Serial ADC 16-Bit, 250ksps 1-/2-Channel Serial ADCs 5V or 5V Supply, 4.096V or 2.5V Span 3V, 15mW, Unipolar Inputs, MSOP Package 3V, 15mW, Bipolar Inputs, MSOP Package 5V, Selectable Spans, 115mW 3V, 14mW, 2-Channel Unipolar Input Range 3V, 14mW, 2-Channel Bipolar Input Range 3V, 15mW, Selectable Bipolar (Unipolar Input, Six Differential Inputs) 5V, Selectable Spans, 80dB SINAD 5V Supply, 2.5V Span, 72dB SINAD 5V, Selectable Spans, 72dB SINAD 5V Supply, 2.5V Span, 90dB SINAD 5V Configurable Bipolar/Unipolar Inputs 5V or 3V (L-Version), Micropower, MSOP Package DESCRIPTION COMMENTS
LTC1403-1/LTC1403A-1 12-/14-Bit, 2.8Msps Serial ADC
LTC1407-1/LTC1407A-1 12-/14-Bit, 3Msps Simultaneous Sampling ADC
SoftSpan is a trademark of Linear Technology Corporation.
TYPICAL APPLICATIO
Low-Jitter Clock Timing with RF Sine Generator Using Clock Squaring/Level Shifting Circuit and Re-Timing Flip-Flop
VCC 1k NC7SVU04P5X MASTER CLOCK VCC CONTROL LOGIC (FPGA, CPLD, DSP, ETC.) Q CONV Q CLR NL17SZ74 CONVERT ENABLE
1408 TA02
0.1F
50
20
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
FAX: (408) 434-0507 www.linear.com
U
1k PRE D LTC 1408-12
140812f LT/LWI 1006 * PRINTED IN THE USA (c) LINEAR TECHNOLOGY CORPORATION 2006

▲Up To Search▲

Price & Availability of LTC1408CUH-12

	To Download LTC1408CUH-12 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .